1. Field of the Invention
The invention relates to processing systems and particularly to scheduling execution of operations in a superscalar processor.
2. Description of Related Art
Instruction sets for reduced instruction set computer (RISC) processors are generally limited to simple instructions that can be executed in relatively few processor clock cycles. RISC instruction sets are also limited so that most instructions require the same number of clock cycles for execution. This simplifies execution units that execute the instructions and circuitry that controls instruction pipelines during execution of a program. The simplification of this circuitry often decreases circuit area and cost of a RISC processor and allows the processor to operate at a higher clock rate.
Complex instruction set computer (CISC) processors have instruction sets that include both simple and complex instructions. Accordingly, it is often difficult or impractical to implement execution of the complex instructions in the same number of clock cycles as the simpler instructions. Conventionally, handling instructions that require different numbers of clock cycles to complete is more complex than handling instructions that require the same number of clock cycles.
Schedulers, execution pipelines, and execution units that directly execute CISC instructions must account for the different execution times. This can increase circuit complexity and area and can reduce overall performance.
An alternative architecture for a CISC processor includes a CISC instruction decoder and a RISC processing core. With this architecture, the CISC instruction decoder coverts each CISC instruction into one or more RISC-type operations that the RISC processing core executes. Typically, the RISC processing core has less complex and faster circuitry that operates at higher frequency and executes more instructions per clock cycle than could a conventional CISC processing core which directly executed the CISC instructions.
U.S. patent application Ser. No. 08/590,383, now abandoned, describes a superscalar processor having a RISC processing core. A scheduler in the processing core schedules operations for execution by multiple execution units including a load unit, a store unit, and two register units. The register units execute "register" operations that, when completed and committed, manipulate the contents of a register file of the processor. The register operations do not require data input or output from outside the processor. For other types of RISC operations executed by such a processor, other execution units can be added, and the scheduler can be expanded to add independent pipelines for the new execution units. However, this increases the complexity of the scheduler and may not provide a proportional increase in processor performance. For example, adding separate pipelines for specific types of operations does not greatly increase number of operations executed per cycle if those types of operations are rare in the code executed. In particular, in code executing many floating-point or multi-media arithmetic operations, register operations that perform integer arithmetic may be relatively rare so that a processing circuit for register operations is often empty or under utilized. Similarly, in code executing many register operations, floating-point or multimedia operations may be relatively rare, and a processing circuit for floating-point or multimedia operations may be often empty or under utilized. Accordingly, to reduce scheduler complexity without a significant performance penalty, it is desirable in some cases, to have different types of operations share the same scheduling pipeline. However, a difficulty arises when the instructions sharing a scheduling pipeline require different numbers of cycles for execution. Methods and systems for adding operations having different numbers of execution cycles to the same scheduling pipeline are sought.